1. Field of the Invention
The present invention relates to a method of fabricating a nonvolatile semiconductor memory of the type that writes and erases data by electron tunneling.
2. Description of the Related Art
A memory cell in this type of memory has a floating gate electrode, a control gate electrode, a thin gate oxide film that insulates the floating gate electrode from the silicon substrate of the cell, and a still thinner tunnel oxide film occupying a window in the gate oxide film. Data are written and erased by moving electrons into and out of the floating gate electrode through the thin tunnel oxide film. Common examples of memories with this structure include electrically erasable and programmable read-only memories (EEPROM).
The tunnel oxide film in an EEPROM of this type is generally fabricated by photolithography and oxidation in the following steps: an oxide film with a thickness slightly less than the desired thickness of the gate oxide film is formed on the substrate; a resist mask with an opening is formed; the oxide film is wet-etched through the opening with hydrofluoric acid or buffered hydrofluoric acid to form the tunnel window; the resist mask is removed; the exposed substrate is cleaned and then thermally oxidized, forming the tunnel oxide film at the bottom of the tunnel window.
Wet etching has the advantage of not damaging the substrate surface, so that a tunnel oxide film of good quality can be formed. However, wet etching also has the disadvantage of being isotropic: etching proceeds laterally, parallel to the substrate, as well as forward toward the substrate, so that the tunnel window becomes larger than the opening in the resist mask. To form a tunnel window of a given size, it is therefore necessary to use photolithographic equipment with a significantly higher resolution than the window dimensions.
EEPROM circuits and other circuits comprising metal-oxide-semiconductor (MOS) transistors are often combined in the same device, the EEPROM memory cells and the MOS transistors having similar dimensions. An ongoing trend in semiconductor fabrication technology is to shorten the gate length of MOS transistors to increase their operating speed. Since the floating and control gates in the EEPROM memory cells are similarly shortened, the size of the tunnel windows in the EEPROM must be reduced to match the gate length of the MOS transistors. Because of the lateral expansion of the tunnel windows during wet etching, it becomes necessary to use photolithographic equipment with a higher resolution than is needed to form the MOS transistors. This is costly and inefficient, but it would also be costly and inefficient to use two different photolithographic processes: one to form the MOS transistors, and another to form the tunnel windows.
In an EEPROM fabrication method described in Japanese Patent Application Publication No. 2002-100688, for example, (paragraphs 0016–0018 and FIG. 3), instead of a wet etching process, a dry anisotropic plasma etching process is used to form the tunnel windows. This enables tunnel windows to be created with the same dimensions as the openings in the resist mask, so higher-resolution photolithographic equipment is not needed, but plasma etching damages the substrate surface. The tunnel oxide film formed on the substrate surface is therefore of poor quality and is susceptible to dielectric breakdown, which allows unwanted charge to leak between the floating gate and substrate when an electric field is applied from the control gate.